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Design of high-performance microprocessor circuits / Anantha Chandrakasan, William J. Bowhill, Frank Fox, [editors].

Contributor(s): Material type: TextTextPublisher: New York : IEEE Press, [2001]Copyright date: ©2001Description: xx, 557 pages : illustrations ; 26 cmContent type:
  • text
Media type:
  • unmediated
Carrier type:
  • volume
ISBN:
  • 078036001X
  • 9780780360013
Subject(s): DDC classification:
  • 621.3815
LOC classification:
  • TK7895.M5 D47 2001
Contents:
Preface -- Part I. Overview -- Chapter 1. Impact of Physical Technology on Architecture -- Part II. Technology Issues -- Chapter 2. CMOS Scaling and Issues in Sub-0.25 [mu]m Systems -- Chapter 3. Techniques for Leakage Power Reduction -- Chapter 4. Low-Voltage Technologies -- Chapter 5. Soi Technology and Circuits -- Chapter 6. Models of Process Variations in Device and Interconnect -- Part III. Circuit Styles for Logic -- Chapter 7. Basic Logic Families -- Chapter 8. Issues in Dynamic Logic Design -- Chapter 9. Self-Timed Pipelines -- Chapter 10. High-Speed VLSI Airthmetic Units: Adders and Multipliers -- Part IV. Clocking -- Chapter 11. Clocked Storage Elements -- Chapter 12. Design of High-Speed CMOS PLLs and DLLs -- Chapter 13. Clock Distribution -- Part V. Memory System Design -- Chapter 14. Register Files and Chahes -- Chapter 15. Embedded Dram -- Part VI. Interconnect and I/O -- Chapter 16. Analyzing on-Chip Interconnect Effects -- Chapter 17. Techniques for Driving Interconnect -- Chapter 18. I/O and ESD Circuit Design -- Chapter 19. High-Speed Electrical Signaling -- Part VII. Reliability -- Chapter 20. Electromigration Reliability -- Chapter 21. Hot Carrier Reliability -- Part VIII. Cad Tools and Test -- Chapter 22. Overview of Computer-Aided Design Tools -- Chapter 23. Timing Verification -- Chapter 24. Design and Analysis of Power Distribution Networks -- Chapter 25. Testing of High-Performance Processors -- Index.
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Holdings
Item type Current library Call number Copy number Status Date due Barcode
Book City Campus City Campus Main Collection 621.3815 DES (Browse shelf(Opens below)) 1 Available A253784B

Includes bibliographical references and index.

Preface -- Part I. Overview -- Chapter 1. Impact of Physical Technology on Architecture -- Part II. Technology Issues -- Chapter 2. CMOS Scaling and Issues in Sub-0.25 [mu]m Systems -- Chapter 3. Techniques for Leakage Power Reduction -- Chapter 4. Low-Voltage Technologies -- Chapter 5. Soi Technology and Circuits -- Chapter 6. Models of Process Variations in Device and Interconnect -- Part III. Circuit Styles for Logic -- Chapter 7. Basic Logic Families -- Chapter 8. Issues in Dynamic Logic Design -- Chapter 9. Self-Timed Pipelines -- Chapter 10. High-Speed VLSI Airthmetic Units: Adders and Multipliers -- Part IV. Clocking -- Chapter 11. Clocked Storage Elements -- Chapter 12. Design of High-Speed CMOS PLLs and DLLs -- Chapter 13. Clock Distribution -- Part V. Memory System Design -- Chapter 14. Register Files and Chahes -- Chapter 15. Embedded Dram -- Part VI. Interconnect and I/O -- Chapter 16. Analyzing on-Chip Interconnect Effects -- Chapter 17. Techniques for Driving Interconnect -- Chapter 18. I/O and ESD Circuit Design -- Chapter 19. High-Speed Electrical Signaling -- Part VII. Reliability -- Chapter 20. Electromigration Reliability -- Chapter 21. Hot Carrier Reliability -- Part VIII. Cad Tools and Test -- Chapter 22. Overview of Computer-Aided Design Tools -- Chapter 23. Timing Verification -- Chapter 24. Design and Analysis of Power Distribution Networks -- Chapter 25. Testing of High-Performance Processors -- Index.

Machine converted from AACR2 source record.

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