000			09085cam a2200373 i 4500
005			20221102163419.0
008			110926s2011 nyua b 001 0 eng d
011			_aBIB MATCHES WORLDCAT
020			_a1441996915 _qhbk.
020			_a9781441996916 _qhbk.
035			_a(ATU)b12194475
035			_a(OCoLC)751823201
040			_aUKMGB _beng _erda _cUKMGB _dCDX _dATU
050		4	_aTK
082	0	4	_a621.3815 _222
100	1		_aShafique, Muhammad, _eauthor. _91089925
245	1	0	_aHardware/software architectures for low-power embedded multimedia systems / _cby Muhammad Shafique, Jörg Henkel.
264		1	_aNew York ; _aLondon : _bSpringer, _c2011.
300			_axxi, 223 pages : _billustrations ; _c24 cm
336			_atext _btxt _2rdacontent
337			_aunmediated _bn _2rdamedia
338			_avolume _bnc _2rdacarrier
504			_aIncludes bibliographical references and index.
505	0	0	_g1. _tIntroduction -- _g1.1. _tTrends and Requirements of Advanced Multimedia Systems -- _g1.2. _tTrends and Options for Multimedia Processing -- _g1.3. _tSummary of Challenges and Issues -- _g1.4. _tContribution of this Monograph -- _g1.5. _tMonograph Outline -- _g2. _tBackground and Related Work -- _g2.1. _tVideo Coding: Basics and Terminology -- _g2.2. _tThe H.264 Advanced Video Codec: A Low-power Perspective -- _g2.2.1. _tOverview of the H.264 Video Encoder and Its Functional Blocks -- _g2.2.2. _tLow-Power Architectures for H.264 /AVC Video Encoder -- _g2.2.3. _tAdaptive and Low-Power Design of the Key Functional Blocks of the H.264 Video Encoder: State-of-the-Art and Their Limitations -- _g2.3. _tReconfigurable Processors -- _g2.3.1. _tFine-Grained Reconfigurable Fabric -- _g2.3.2. _tLeakage Power of Fine-grained Reconfigurable Fabric and the Power-Shutdown Infrastructure -- _g2.3.3. _tCustom Instructions (CIs): A Reconfigurable Processor Perspective -- _g2.3.4. _tReconfigurable Instruction Set Processors -- _g2.3.5. _tRotating Instruction Set Processing Platform (RISPP) -- _g2.4. _tLow-Power Approaches in Reconfigurable Processors -- _g2.5. _tSummary of Related Work -- _g3. _tAdaptive Low-Power Architectures for Embedded Multimedia Systems -- _g3.1. _tAnalyzing the Video Coding Application for Energy Consumption and Adaptivity -- _g3.1.1. _tAdvanced Video Codecs: Analyzing the Tool Set -- _g3.1.2. _tEnergy and Adaptivity Related Issues in H.264 /AVC Video Encoder -- _g3.2. _tEnergy- and Adaptivity Related Issues for Dynamically Reconfigurable Processors -- _g3.3. _tOverview of the Proposed Architectures and Design Steps -- _g3.4. _tPower Model for Dynamically Reconfigurable Processors -- _g3.4.1. _tPower Consuming Parts of a Computation- and Communication-Infrastructure in a Dynamically Reconfigurable Processor -- _g3.4.2. _tThe Proposed Power Model -- _g3.5. _tSummary of Adaptive Low-Power Embedded Multimedia System -- _g4. _tAdaptive Low-Power Video Coding -- _g4.1. _tH.264 Encoder Application Architectural Adaptations for Reconfigurable Processors -- _g4.1.1. _tBasic Application Architectural Adaptations -- _g4.1.2. _tApplication Architectural Adaptations for On-Demand Interpolation -- _g4.1.3. _tApplication Architectural Adaptations for Reducing the Hardware Pressure -- _g4.1.4. _tData Flow of the H.264 Encoder Application Architecture with Reduced Hardware Pressure -- _g4.2. _tDesigning Low-Power Data Paths and Custom Instructions -- _g4.2.1. _tDesigning the Custom Instruction for In-Loop Deblocking Filter -- _g4.2.2. _tDesigning the Custom Instructions for Motion Estimation -- _g4.2.3. _tDesigning the Custom Instruction for Motion Compensation -- _g4.2.4. _tArea Results for the Custom Instructions of H.264 Encoder -- _g4.3. _tSpatial and Temporal Analysis of Videos Considering Human Visual System -- _g4.3.1. _tHVS-based Macroblock Categorization -- _g4.3.2. _tQP-based Thresholding -- _g4.3.3. _tSummary of Spatial and Temporal Analysis of Videos Considering Human Visual System -- _g4.4. _tAn HVS-Based Adaptive Complexity Reduction Scheme -- _g4.4.1. _tPrognostic Early Mode Exclusion -- _g4.4.2. _tHierarchical Fast Mode Prediction -- _g4.4.3. _tSequential RDO Mode Elimination -- _g4.4.4. _tEvaluation of the Complexity Reduction Scheme -- _g4.5. _tEnergy-Aware Motion Estimation with an Integrated Energy-Budgeting Scheme -- _g4.5.1. _tAdaptive Motion Estimator with Multiple Processing Stages -- _g4.5.2. _tenBudget: The Adaptive Predictive Energybudgeting Scheme -- _g4.5.3. _tEvaluation of Energy-Aware Motion Estimation with an Integrated Energy-Budgeting Scheme -- _g4.5.4. _tComparing Adaptive Motion Estimator with and Without the enBudget Scheme -- _g4.5.5. _tComparing UMHexagonS with and Without the enBudget Scheme -- _g4.6. _tSummary of Low-power Application Architecture -- _g5. _tAdaptive Low-power Reconfigurable Processor Architecture -- _g5.1. _tMotivational Scenario and Problem Identification -- _g5.1.1. _tSummary of the Motivational Scenario and Problem Identification -- _g5.2. _tRun-time Adaptive Energy Management with the Novel Concept of Custom Instruction Set Muting -- _g5.2.1. _tConcept of Muting the Custom Instructions -- _g5.2.2. _tPower-shutdown Infrastructure for the Muted Custom Instructions -- _g5.2.3. _tRun-time Adaptive Energy Management -- _g5.2.4. _tSummary of the Run-time Adaptive Energy Management and CI Muting -- _g5.3. _tDetermining an Energy-minimizing Instruction Set -- _g5.3.1. _tFormal Problem Modeling and Energy Benefit Function -- _g5.3.2. _tAlgorithm for Choosing CI Implementation Versions -- _g5.3.3. _tEvaluation and Results for Energy-Minimizing Instruction Set -- _g5.3.4. _tSummary of Energy Minimizing Instruction Set -- _g5.4. _tSelective Instruction Set Muting -- _g5.4.1. _tProblem Description and Motivational Scenarios -- _g5.4.2. _tOperational Flow for Selective Instruction Set Muting -- _g5.4.3. _tAnalyzing the Energy Benefit Function of Muting -- _g5.4.4. _tHot Spot Requirement Prediction: Computing Weighting Factors for CIs -- _g5.4.5. _tEvaluation of Selective Instruction Set Muting -- _g5.3.6. _tSummary of Selective Instruction Set Muting -- _g5.5. _tSummary of Adaptive Low-power Reconfigurable Processor Architecture -- _g6. _tPower Measurement of the Reconfigurable Processors -- _g6.1. _tPower Measurement Setup -- _g6.2. _tMeasuring the Power of Custom Instructions -- _g6.2.1. _tFlow for Creating the Power Model -- _g6.2.2. _tTest Cases for Power Measurements -- _g6.2.3. _tResults for Power Measurement and Estimation -- _g6.3. _tMeasuring the Power of the Reconfiguration Process -- _g6.3.1. _tPower Consumption of EEPROM -- _g6.3.2. _tPower Consumption of the Reconfiguration via ICAP -- _g6.4. _tSummary of the Power Measurement of the Reconfigurable Processors -- _g7. _tBenchmarks and Results -- _g7.1. _tSimulation Conditions and Fairness of the Comparison -- _g7.2. _tAdaptive Low-power Application Architecture -- _g7.2.1. _tComparing Complexity Reduction Scheme to State-of-the-art and the Exhaustive RDO-MD -- _g7.2.2. _tComparing the Energy-Aware Motion Estimation with Integrated Energy Budgeting Scheme to Stateof- the-art -- _g7.3. _tAdaptive Low-power Processor Architecture -- _g7.3.1. _tComparing the Adaptive Energy Management Scheme (Without Selective Instruction Set Muting) to RISPP with Performance Maximization [BSH08c] -- _g7.3.2. _tApplying the Adaptive Energy Management Scheme (Without Selective Instruction Set Muting) to Molen [VWG + 04] Reconfigurable Processor -- _g7.3.3. _tComparing the Adaptive Energy Management Scheme (with Selective Instruction Set Muting) to State-of-the-art Hardware-oriented Shutdown -- _g7.4. _tSummary of the Benchmarks and Comparisons -- _g8. _tConclusion and Outlook -- _g8.1. _tMonograph Summary -- _g8.2. _tFuture Work.
520			_a"The extreme complexity/energy requirements and context-aware processing nature of multimedia applications stimulate the need for adaptive low-power embedded multimedia systems with high-performance. Run-time adaptivity is required to react to the run-time varying scenarios (e.g., quality and performance constraints, available energy, input data). This book presents techniques for energy reduction in adaptive embedded multimedia systems, based on dynamically reconfigurable processors. The approach described will enable designers to meet performance/area constraints, while minimizing video quality degradation, under various, run-time scenarios. Emphasis is placed on implementing power/energy reduction at various abstraction levels. To enable this, novel techniques for adaptive energy management at both processor architecture and application architecture levels are presented, such that both hardware and software adapt together, minimizing overall energy consumption under unpredictable, design-/compile-time scenarios."--Publisher's website.
588			_aMachine converted from AACR2 source record.
650		0	_aLow voltage integrated circuits _9328415
650		0	_aEmbedded computer systems _xDesign and construction _9786165
700	1		_aHenkel, J. _q(Jörg), _eauthor. _9274724
907			_a.b12194475 _b22-08-17 _c28-10-15
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998			_ab _ac _b06-04-16 _cm _da _feng _gnyu _h0
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