000 | 02990cam a22004214i 4500 | ||
---|---|---|---|
005 | 20221101192844.0 | ||
008 | 000324s2001 nyua b 001 0 eng d | ||
010 | _a 00036977 | ||
011 | _aBIB MATCHES WORLDCAT | ||
020 | _a078036001X | ||
020 | _a9780780360013 | ||
035 | _a(ATU)b10685054 | ||
035 | _a(DLC) 00036977 | ||
035 | _a(OCoLC)43884738 | ||
040 |
_aDLC _beng _erda _dATU |
||
042 | _apcc | ||
050 | 0 | 0 |
_aTK7895.M5 _bD47 2001 |
082 | 0 | _a621.3815 | |
245 | 0 | 0 |
_aDesign of high-performance microprocessor circuits / _cAnantha Chandrakasan, William J. Bowhill, Frank Fox, [editors]. |
264 | 1 |
_aNew York : _bIEEE Press, _c[2001] |
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264 | 4 | _c©2001 | |
300 |
_axx, 557 pages : _billustrations ; _c26 cm |
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336 |
_atext _btxt _2rdacontent |
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337 |
_aunmediated _bn _2rdamedia |
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338 |
_avolume _bnc _2rdacarrier |
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504 | _aIncludes bibliographical references and index. | ||
505 | 0 | 0 |
_tPreface -- _gPart I. _tOverview -- _gChapter 1. _tImpact of Physical Technology on Architecture -- _gPart II. _tTechnology Issues -- _gChapter 2. _tCMOS Scaling and Issues in Sub-0.25 [mu]m Systems -- _gChapter 3. _tTechniques for Leakage Power Reduction -- _gChapter 4. _tLow-Voltage Technologies -- _gChapter 5. _tSoi Technology and Circuits -- _gChapter 6. _tModels of Process Variations in Device and Interconnect -- _gPart III. _tCircuit Styles for Logic -- _gChapter 7. _tBasic Logic Families -- _gChapter 8. _tIssues in Dynamic Logic Design -- _gChapter 9. _tSelf-Timed Pipelines -- _gChapter 10. _tHigh-Speed VLSI Airthmetic Units: Adders and Multipliers -- _gPart IV. _tClocking -- _gChapter 11. _tClocked Storage Elements -- _gChapter 12. _tDesign of High-Speed CMOS PLLs and DLLs -- _gChapter 13. _tClock Distribution -- _gPart V. _tMemory System Design -- _gChapter 14. _tRegister Files and Chahes -- _gChapter 15. _tEmbedded Dram -- _gPart VI. _tInterconnect and I/O -- _gChapter 16. _tAnalyzing on-Chip Interconnect Effects -- _gChapter 17. _tTechniques for Driving Interconnect -- _gChapter 18. _tI/O and ESD Circuit Design -- _gChapter 19. _tHigh-Speed Electrical Signaling -- _gPart VII. _tReliability -- _gChapter 20. _tElectromigration Reliability -- _gChapter 21. _tHot Carrier Reliability -- _gPart VIII. _tCad Tools and Test -- _gChapter 22. _tOverview of Computer-Aided Design Tools -- _gChapter 23. _tTiming Verification -- _gChapter 24. _tDesign and Analysis of Power Distribution Networks -- _gChapter 25. _tTesting of High-Performance Processors -- _tIndex. |
588 | _aMachine converted from AACR2 source record. | ||
650 | 0 |
_aMicroprocessors _xDesign and construction _9786413 |
|
650 | 0 |
_aLogic circuits _9320210 |
|
700 | 1 |
_aChandrakasan, Anantha P. _91042786 |
|
700 | 1 |
_aBowhill, William J. _91042787 |
|
700 | 1 |
_aFox, Frank, _d1952- _9224829 |
|
907 |
_a.b10685054 _b11-07-17 _c27-10-15 |
||
942 | _cB | ||
945 |
_a621.3815 DES _g1 _iA253784B _j0 _lcmain _o- _p$298.77 _q- _r- _s- _t0 _u1 _v0 _w0 _x0 _y.i11663479 _z28-10-15 |
||
998 |
_a(2)b _a(2)c _b06-04-16 _cm _da _feng _gnyu _h0 |
||
999 |
_c1137030 _d1137030 |