Hardware/software architectures for low-power embedded multimedia systems / by Muhammad Shafique, Jörg Henkel.

Includes bibliographical references and index.

1. Introduction -- 1.1. Trends and Requirements of Advanced Multimedia Systems -- 1.2. Trends and Options for Multimedia Processing -- 1.3. Summary of Challenges and Issues -- 1.4. Contribution of this Monograph -- 1.5. Monograph Outline -- 2. Background and Related Work -- 2.1. Video Coding: Basics and Terminology -- 2.2. The H.264 Advanced Video Codec: A Low-power Perspective -- 2.2.1. Overview of the H.264 Video Encoder and Its Functional Blocks -- 2.2.2. Low-Power Architectures for H.264 /AVC Video Encoder -- 2.2.3. Adaptive and Low-Power Design of the Key Functional Blocks of the H.264 Video Encoder: State-of-the-Art and Their Limitations -- 2.3. Reconfigurable Processors -- 2.3.1. Fine-Grained Reconfigurable Fabric -- 2.3.2. Leakage Power of Fine-grained Reconfigurable Fabric and the Power-Shutdown Infrastructure -- 2.3.3. Custom Instructions (CIs): A Reconfigurable Processor Perspective -- 2.3.4. Reconfigurable Instruction Set Processors -- 2.3.5. Rotating Instruction Set Processing Platform (RISPP) -- 2.4. Low-Power Approaches in Reconfigurable Processors -- 2.5. Summary of Related Work -- 3. Adaptive Low-Power Architectures for Embedded Multimedia Systems -- 3.1. Analyzing the Video Coding Application for Energy Consumption and Adaptivity -- 3.1.1. Advanced Video Codecs: Analyzing the Tool Set -- 3.1.2. Energy and Adaptivity Related Issues in H.264 /AVC Video Encoder -- 3.2. Energy- and Adaptivity Related Issues for Dynamically Reconfigurable Processors -- 3.3. Overview of the Proposed Architectures and Design Steps -- 3.4. Power Model for Dynamically Reconfigurable Processors -- 3.4.1. Power Consuming Parts of a Computation- and Communication-Infrastructure in a Dynamically Reconfigurable Processor -- 3.4.2. The Proposed Power Model -- 3.5. Summary of Adaptive Low-Power Embedded Multimedia System -- 4. Adaptive Low-Power Video Coding -- 4.1. H.264 Encoder Application Architectural Adaptations for Reconfigurable Processors -- 4.1.1. Basic Application Architectural Adaptations -- 4.1.2. Application Architectural Adaptations for On-Demand Interpolation -- 4.1.3. Application Architectural Adaptations for Reducing the Hardware Pressure -- 4.1.4. Data Flow of the H.264 Encoder Application Architecture with Reduced Hardware Pressure -- 4.2. Designing Low-Power Data Paths and Custom Instructions -- 4.2.1. Designing the Custom Instruction for In-Loop Deblocking Filter -- 4.2.2. Designing the Custom Instructions for Motion Estimation -- 4.2.3. Designing the Custom Instruction for Motion Compensation -- 4.2.4. Area Results for the Custom Instructions of H.264 Encoder -- 4.3. Spatial and Temporal Analysis of Videos Considering Human Visual System -- 4.3.1. HVS-based Macroblock Categorization -- 4.3.2. QP-based Thresholding -- 4.3.3. Summary of Spatial and Temporal Analysis of Videos Considering Human Visual System -- 4.4. An HVS-Based Adaptive Complexity Reduction Scheme -- 4.4.1. Prognostic Early Mode Exclusion -- 4.4.2. Hierarchical Fast Mode Prediction -- 4.4.3. Sequential RDO Mode Elimination -- 4.4.4. Evaluation of the Complexity Reduction Scheme -- 4.5. Energy-Aware Motion Estimation with an Integrated Energy-Budgeting Scheme -- 4.5.1. Adaptive Motion Estimator with Multiple Processing Stages -- 4.5.2. enBudget: The Adaptive Predictive Energybudgeting Scheme -- 4.5.3. Evaluation of Energy-Aware Motion Estimation with an Integrated Energy-Budgeting Scheme -- 4.5.4. Comparing Adaptive Motion Estimator with and Without the enBudget Scheme -- 4.5.5. Comparing UMHexagonS with and Without the enBudget Scheme -- 4.6. Summary of Low-power Application Architecture -- 5. Adaptive Low-power Reconfigurable Processor Architecture -- 5.1. Motivational Scenario and Problem Identification -- 5.1.1. Summary of the Motivational Scenario and Problem Identification -- 5.2. Run-time Adaptive Energy Management with the Novel Concept of Custom Instruction Set Muting -- 5.2.1. Concept of Muting the Custom Instructions -- 5.2.2. Power-shutdown Infrastructure for the Muted Custom Instructions -- 5.2.3. Run-time Adaptive Energy Management -- 5.2.4. Summary of the Run-time Adaptive Energy Management and CI Muting -- 5.3. Determining an Energy-minimizing Instruction Set -- 5.3.1. Formal Problem Modeling and Energy Benefit Function -- 5.3.2. Algorithm for Choosing CI Implementation Versions -- 5.3.3. Evaluation and Results for Energy-Minimizing Instruction Set -- 5.3.4. Summary of Energy Minimizing Instruction Set -- 5.4. Selective Instruction Set Muting -- 5.4.1. Problem Description and Motivational Scenarios -- 5.4.2. Operational Flow for Selective Instruction Set Muting -- 5.4.3. Analyzing the Energy Benefit Function of Muting -- 5.4.4. Hot Spot Requirement Prediction: Computing Weighting Factors for CIs -- 5.4.5. Evaluation of Selective Instruction Set Muting -- 5.3.6. Summary of Selective Instruction Set Muting -- 5.5. Summary of Adaptive Low-power Reconfigurable Processor Architecture -- 6. Power Measurement of the Reconfigurable Processors -- 6.1. Power Measurement Setup -- 6.2. Measuring the Power of Custom Instructions -- 6.2.1. Flow for Creating the Power Model -- 6.2.2. Test Cases for Power Measurements -- 6.2.3. Results for Power Measurement and Estimation -- 6.3. Measuring the Power of the Reconfiguration Process -- 6.3.1. Power Consumption of EEPROM -- 6.3.2. Power Consumption of the Reconfiguration via ICAP -- 6.4. Summary of the Power Measurement of the Reconfigurable Processors -- 7. Benchmarks and Results -- 7.1. Simulation Conditions and Fairness of the Comparison -- 7.2. Adaptive Low-power Application Architecture -- 7.2.1. Comparing Complexity Reduction Scheme to State-of-the-art and the Exhaustive RDO-MD -- 7.2.2. Comparing the Energy-Aware Motion Estimation with Integrated Energy Budgeting Scheme to Stateof- the-art -- 7.3. Adaptive Low-power Processor Architecture -- 7.3.1. Comparing the Adaptive Energy Management Scheme (Without Selective Instruction Set Muting) to RISPP with Performance Maximization [BSH08c] -- 7.3.2. Applying the Adaptive Energy Management Scheme (Without Selective Instruction Set Muting) to Molen [VWG + 04] Reconfigurable Processor -- 7.3.3. Comparing the Adaptive Energy Management Scheme (with Selective Instruction Set Muting) to State-of-the-art Hardware-oriented Shutdown -- 7.4. Summary of the Benchmarks and Comparisons -- 8. Conclusion and Outlook -- 8.1. Monograph Summary -- 8.2. Future Work.

"The extreme complexity/energy requirements and context-aware processing nature of multimedia applications stimulate the need for adaptive low-power embedded multimedia systems with high-performance. Run-time adaptivity is required to react to the run-time varying scenarios (e.g., quality and performance constraints, available energy, input data). This book presents techniques for energy reduction in adaptive embedded multimedia systems, based on dynamically reconfigurable processors. The approach described will enable designers to meet performance/area constraints, while minimizing video quality degradation, under various, run-time scenarios. Emphasis is placed on implementing power/energy reduction at various abstraction levels. To enable this, novel techniques for adaptive energy management at both processor architecture and application architecture levels are presented, such that both hardware and software adapt together, minimizing overall energy consumption under unpredictable, design-/compile-time scenarios."--Publisher's website.

Machine converted from AACR2 source record.