Robust computing with nano-scale devices : progresses and challenges / Chao Huang, editor.

Includes bibliographical references and index.

Cover -- Contents -- Introduction -- Fault Tolerant Nanocomputing -- Introduction -- Principles of Fault Tolerant Nanocomputer Systems -- Hardware Redundancy -- N-Modular Redundancy -- NAND Multiplexing -- Reconfiguration -- Information Redundancy -- Time Redundancy -- Coverage -- Process Variations in Nanoscale Circuits -- Fault Tolerant Nanocomputer Applications -- General-Purpose Computing -- Long-Life Applications -- Critical-Computation Applications -- High-Availability Applications -- Maintenance Postponement Applications -- Trends and Future -- References -- Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics -- Introduction -- Previous Approaches -- Defect-Tolerant Techniques -- Defect Avoidance Techniques -- Defect-Tolerant FPGA Design Techniques -- Reliability Analysis -- Proposed Defect Tolerance Technique -- Experimental Results -- Stuck-Open and Stuck-Short Defect Analysis -- Bridging Defect Analysis -- Conclusion -- References -- Fault-Tolerant Design for Nanowire-Based Programmable Logic Arrays -- Introduction -- Background -- Nanowire-Based PLA -- Defect Model -- Redundancy-Based Defect-Tolerant Techniques -- Conventional Redundancy-Based Techniques -- Logic Duplication in PLA -- Defect-Aware Logic Mapping for Nanowire-Based PLA -- Defect-Free Subset Identification -- Defect-Aware Mapping Through Bipartite Graph Embedding -- SAT-Based Defect-Aware Mapping -- Experimental Results -- Conclusions and Perspectives -- References -- Built-In Self-Test and Defect Tolerance for Molecular Electronics-Based NanoFabrics -- Introduction -- NanoFabric Architecture -- Fault Model -- Summary of the Proposed Method -- Related Prior Work -- BIST Procedure -- Test Architectures (TAs) -- Test Procedure -- Test Configurations -- Test Configurations for Detecting Faults in NanoBlocks -- Test Configurations for Detecting Faults in SwitchBlocks -- Number of Test Configurations -- Time Analysis for BIST -- Recovery Analysis -- Simulation and Results -- Discussion -- Conclusion -- References -- The Prospect and Challenges of CNFET Based Circuits: A Physical Insight -- Introduction -- Fundamentals of CNFET -- Compact Model of CNFET -- Impact of Parasitics on Circuit Performance -- Geometry Dependent Parasitic Capacitance -- Analysis of Fringe Capacitance -- Impact of Process Variation -- A Physical Insight to CNFET Characteristics Under Process Variation -- CNFET Performance Under Process Variation -- Summary -- Appendix I: Polynomial Expression of Q[sub(CNT)] -- References -- Computing with Nanowires: A Self Assembled Neuromorphic Architecture -- Introduction -- Self Assembly of Neuromorphic Networks -- Electrical Characterization of the Nanowires -- What Causes the Negative Differential Resistance? -- Other Electrical Parameters -- Simulation Results -- Conclusion -- References -- Computational Opportunities and CAD for Nanotechnologies -- Introduction -- A Holistic CAD Platform for Nanotechnologies -- High-Level Modeling and Simulation Tool (HLMS) -- Artificial Ecosystems -- Spontaneous Creation of Artificial Organisms -- Optimization of Existing Functions -- Acquisition of New Functions -- Systems of Particles and Emergence of.

Machine converted from AACR2 source record.