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The Verilog hardware description language / Donald E. Thomas, Philip R. Moorby.

By: Contributor(s): Material type: TextTextPublisher: Norwell, Mass. : Kluwer Academic Publishers, [2002]Copyright date: ©2002Edition: Fifth editionDescription: xx, 381 pages : illustrations ; 24 cm + 1 computer disc (12 cm)Content type:
  • text
  • computer dataset
Media type:
  • unmediated
  • computer
Carrier type:
  • volume
  • computer disc
ISBN:
  • 1402070896
  • 9781402070891
Other title:
  • Thomas & Moorby's the Verilog hardware description language [Cover title]
Subject(s): DDC classification:
  • 621.395 21
LOC classification:
  • TK7885.7 .T48 2002
Contents:
Preface -- From the Old to the New -- Acknowledgments -- 1. Verilog - A Tutorial Introduction -- 2. Logic Synthesis -- 3. Behavioral Modeling -- 4. Concurrent Processes -- 5. Module Hierarchy -- 6. Logic Level Modeling -- 7. Cycle-Accurate Specification -- 8. Advanced Timing -- 9. User-Defined Primitives -- 10. Switch Level Modeling -- 11. Projects -- App. A: Tutorial Questions and Discussion -- App. B. Lexical Conventions -- App. C. Verilog Operators -- App. D. Verilog Gate Types -- App. E. Registers, Memories, Integers, and Time -- App. F. System Tasks and Functions -- App. G. Formal Syntax Definition -- Index.
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Holdings
Item type Current library Call number Copy number Status Date due Barcode
Book City Campus City Campus Main Collection 621.395 THO (Browse shelf(Opens below)) 1 Available A416976B
Accompanying Material City Campus City Campus Main Collection 621.395 THO Accompanying part (Disc) (Browse shelf(Opens below)) 1 Not for loan A345948B

Includes index.

Accompanied by: 1 computer disc (CD-ROM)

Preface -- From the Old to the New -- Acknowledgments -- 1. Verilog - A Tutorial Introduction -- 2. Logic Synthesis -- 3. Behavioral Modeling -- 4. Concurrent Processes -- 5. Module Hierarchy -- 6. Logic Level Modeling -- 7. Cycle-Accurate Specification -- 8. Advanced Timing -- 9. User-Defined Primitives -- 10. Switch Level Modeling -- 11. Projects -- App. A: Tutorial Questions and Discussion -- App. B. Lexical Conventions -- App. C. Verilog Operators -- App. D. Verilog Gate Types -- App. E. Registers, Memories, Integers, and Time -- App. F. System Tasks and Functions -- App. G. Formal Syntax Definition -- Index.

Machine converted from AACR2 source record.

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